7 #ifndef __MSP430WARE_EUSCI_A_UART_H__ 8 #define __MSP430WARE_EUSCI_A_UART_H__ 10 #include "inc/hw_memmap.h" 12 #ifdef __MSP430_HAS_EUSCI_Ax__ 25 #include "inc/hw_memmap.h" 31 #define DEFAULT_SYNC 0x00 32 #define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55 95 #define EUSCI_A_UART_NO_PARITY 0x00 96 #define EUSCI_A_UART_ODD_PARITY 0x01 97 #define EUSCI_A_UART_EVEN_PARITY 0x02 105 #define EUSCI_A_UART_MSB_FIRST UCMSB 106 #define EUSCI_A_UART_LSB_FIRST 0x00 114 #define EUSCI_A_UART_MODE UCMODE_0 115 #define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1 116 #define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2 117 #define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3 125 #define EUSCI_A_UART_CLOCKSOURCE_UCLK UCSSEL__UCLK 126 #define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK 127 #define EUSCI_A_UART_CLOCKSOURCE_ACLK 0x40 128 #define EUSCI_A_UART_CLOCKSOURCE_MODCLK 0x40 136 #define EUSCI_A_UART_ONE_STOP_BIT 0x00 137 #define EUSCI_A_UART_TWO_STOP_BITS UCSPB 145 #define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 146 #define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 155 #define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE 156 #define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE 157 #define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE 158 #define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE 159 #define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE 160 #define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE 170 #define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG 171 #define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG 172 #define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG 173 #define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG 182 #define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN 183 #define EUSCI_A_UART_FRAMING_ERROR UCFE 184 #define EUSCI_A_UART_OVERRUN_ERROR UCOE 185 #define EUSCI_A_UART_PARITY_ERROR UCPE 186 #define EUSCI_A_UART_BREAK_DETECT UCBRK 187 #define EUSCI_A_UART_RECEIVE_ERROR UCRXERR 188 #define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR 189 #define EUSCI_A_UART_IDLELINE UCIDLE 190 #define EUSCI_A_UART_BUSY UCBUSY 198 #define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00 199 #define EUSCI_A_UART_DEGLITCH_TIME_50ns UCGLIT0 200 #define EUSCI_A_UART_DEGLITCH_TIME_100ns UCGLIT1 201 #define EUSCI_A_UART_DEGLITCH_TIME_200ns (UCGLIT0 + UCGLIT1) 209 #define EUSCI_A_UART_REMAP_PINS_FALSE (0x0000) 210 #define EUSCI_A_UART_REMAP_PINS_TRUE (USCIARMP) 265 uint8_t transmitData);
509 uint8_t transmitAddress);
575 uint16_t deglitchTime);
605 #define EUSCI_A_UART_REMAP_PINS_1 EUSCI_A_UART_REMAP_PINS_FALSE 606 #define EUSCI_A_UART_REMAP_PINS_2 EUSCI_A_UART_REMAP_PINS_TRUE 618 #endif // __MSP430WARE_EUSCI_A_UART_H__ uint8_t overSampling
Definition: eusci_a_uart.h:85
uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress)
Receives a byte that has been sent to the UART Module.
Definition: eusci_a_uart.c:93
uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress)
Returns the address of the RX Buffer of the UART for the DMA module.
Definition: eusci_a_uart.c:210
uint8_t firstModReg
Definition: eusci_a_uart.h:53
void EUSCI_A_UART_transmitAddress(uint16_t baseAddress, uint8_t transmitAddress)
Transmits the next byte to be transmitted marked as address depending on selected multiprocessor mode...
Definition: eusci_a_uart.c:179
void EUSCI_A_UART_transmitBreak(uint16_t baseAddress)
Transmit break.
Definition: eusci_a_uart.c:189
uint8_t parity
Definition: eusci_a_uart.h:63
uint8_t secondModReg
Definition: eusci_a_uart.h:57
uint16_t clockPrescalar
Is the value to be written into UCBRx bits.
Definition: eusci_a_uart.h:49
bool EUSCI_A_UART_init(uint16_t baseAddress, EUSCI_A_UART_initParam *param)
Advanced initialization routine for the UART block. The values to be written into the clockPrescalar...
Definition: eusci_a_uart.c:21
uint16_t numberofStopBits
Definition: eusci_a_uart.h:73
void EUSCI_A_UART_setDormant(uint16_t baseAddress)
Sets the UART module in dormant mode.
Definition: eusci_a_uart.c:169
void EUSCI_A_UART_transmitData(uint16_t baseAddress, uint8_t transmitData)
Transmits a byte from the UART Module.Please note that if TX interrupt is disabled, this function manually polls the TX IFG flag waiting for an indication that it is safe to write to the transmit buffer and does not time-out.
Definition: eusci_a_uart.c:80
void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress, uint8_t mask)
Disables individual UART interrupt sources.
Definition: eusci_a_uart.c:122
uint16_t msborLsbFirst
Definition: eusci_a_uart.h:68
uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress, uint8_t mask)
Gets the current UART interrupt status.
Definition: eusci_a_uart.c:139
void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress, uint16_t mask)
Clears UART interrupt sources.
Definition: eusci_a_uart.c:145
uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress)
Returns the address of the TX Buffer of the UART for the DMA module.
Definition: eusci_a_uart.c:215
void EUSCI_A_UART_resetDormant(uint16_t baseAddress)
Re-enables UART module from dormant mode.
Definition: eusci_a_uart.c:174
void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress, uint16_t deglitchTime)
Sets the deglitch time.
Definition: eusci_a_uart.c:220
void EUSCI_A_UART_disable(uint16_t baseAddress)
Disables the UART block.
Definition: eusci_a_uart.c:157
void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress, uint8_t mask)
Enables individual UART interrupt sources.
Definition: eusci_a_uart.c:104
uint16_t uartMode
Definition: eusci_a_uart.h:80
Used in the EUSCI_A_UART_init() function as the param parameter.
Definition: eusci_a_uart.h:39
uint8_t selectClockSource
Definition: eusci_a_uart.h:47
void EUSCI_A_UART_remapPins(uint16_t baseAddress, uint8_t pinsSelect)
Remaps eUSCI_A GPIO pins.
Definition: eusci_a_uart.c:229
uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress, uint8_t mask)
Gets the current UART status flags.
Definition: eusci_a_uart.c:163
void EUSCI_A_UART_enable(uint16_t baseAddress)
Enables the UART block.
Definition: eusci_a_uart.c:151